The present invention relates to an input circuit, and, more particularly, to an input circuit that amplifies an external input signal having a relatively small amplitude and an external clock signal.
With the higher speed and the lower power consumption of todays computer systems, lower power supply voltages are also required by the semiconductor devices inside the systems. Consequently, the amplitude of a signal provided to the semiconductor devices has been reduced. Therefore, in order to efficiently amplify the small amplitude signal, the semiconductor devices includes an input circuit which receives power from an internal power supply, which steps up or steps down voltages of an external power supply.
As shown in FIG. 1, a conventional input circuit 50 comprises a first differential amplifier 51, a second differential amplifier 52 and a latch circuit 53. Power is supplied to the first differential amplifier 51 from a high potential power supply Vdd and a low potential power supply Vss. The first differential amplifier 51 receives an external clock signal EXCLK and a reference voltage Vref. The first differential amplifier 51 amplifies the external clock signal EXCLK using the reference voltage Vref as a threshold, and provides the latch circuit 53 with a clock signal CLK having an amplitude equal to the potential difference between the power supplies Vdd and Vcc. As shown in FIGS. 2(a) and 2(b), the first differential amplifier 51 amplifies the external clock signal EXCLK having relatively small amplitude to generate the clock signal CLK.
Referring back to FIG. 1, power is supplied to the second differential amplifier 52 from the high potential power supply Vdd and a step-down voltage power supply Vssi produced by stepping down the voltage of the low potential power supply Vss with a step down voltage circuit (not illustrated). The second differential amplifier 52 receives an external input signal EXin and the reference voltage Vref. The second differential amplifier 52 amplifies the external input signal EXin using the reference voltage Vref as the threshold, and provides the latch circuit 53 with an input signal Sin having an amplitude equal to the potential difference between the power supplies Vdd and Vssi. The second differential amplifier 52 produces the amplified input signal Sin by amplifying the external input signal EXin, which has a relatively small amplitude.
The latch circuit 53 receives the input signal Sin from the second differential amplifier 52 and latches it in response to the rising of the clock signal CLK from the first differential amplifier 51. Then, the latch circuit 53 provides the latched input signal Sin, as an output signal Sout, to a next stage (not illustrated).
As shown in FIGS. 2(a) and 2(c), the clock signal CLK is delayed by an operating delay time t1 of the first differential amplifier 51 with respect to the external clock signal EXCLK. Similarly, the input signal Sin is delayed by an operating delay time t2 of the second differential amplifier 52 with respect to the external input signal EXin. However, although the operating delay time t1 of the differential amplifier 51 is constant, the operating delay time t2 of the differential amplifier 52 varies. In this case, the delay time t2 gradually increases.
Specifically, since the power supplies Vdd and Vss supplied to the first differential amplifier 51 are generally stable, the drive capability of the first differential amplifier 51 does not vary. However, the step-down voltage power supply Vssi produced by the step down voltage circuit is unstable. As shown in FIG. 2(e), the voltage level of the step-down voltage power supply Vssi gradually increases, so that the drive capability of the second differential amplifier 52 gradually decreases. Therefore, the operating delay time t2 of the second differential amplifier 52 gradually increases. As a result, a phase shift occurs between the clock signal CLK and the input signal Sin. With the variation of the step-down voltage power supply Vssi, the level of the amplified input, signal Sin can also vary, although the variation does not affect the operation of the input circuit 50.
When the relative relationship between the clock signal CLK and the input signal Sin is changed, the latch circuit 53 may not receive the input signal Sin correctly in response to the rising of the clock signal CLK, in which case, the latch circuit 53 outputs the incorrect output signal Sout.
The object of the present invention is to provide an input circuit which decreases the phase lag between a clock signal and an input signal.